pll103-02 ddr sdram buffer for desktop pcs with 4 ddr dimms 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 11/07/00 page 1 features generates 24 output buffer from one input. supports up to four ddr dimms or 2 sdram dimms. supports 266mhz ddr sdram. one additional output for feedback. less than 5ns delay. skew between any outputs is less than 100 ps. 2.5v or 3.3v supply range. enhanced ddr and sdram output drive selected by i2c. available in 48 pin ssop. block diagram pin configuration note: #: active low descriptions the pll103-02 is designed as a 3.3v/2.5v buffer to distribute high-speed clocks in pc applications. the device has 24 outputs. these outputs can be configured to support four unbuffered ddr dimms or to support 2 unbuffered standard sdram dimms and 2 ddr dimms. the pll103-02 can be used in conjunction with the pll202-04 or similar clock synthesizer for the via pro 266 chipset. the pll103-02 also has an i2c interface, which can enable or disable each output clock. when power up, all output clocks are enabled (has internal pull up). pll103-02 ddr5c ddr4c_sdram7 ddr4t_sdram6 gnd vdd3.3_2.5 ddr3c_sdram5 ddr3t_sdram4 gnd vdd3.3_2.5 ddr2c_sdram3 gnd vdd3.3_2.5 ddr1c_sdram1 ddr0c ddr0t gnd vdd3.3_2.5 fbout sdata vdd3.3_2.5 ddr5t ddr2t_sdram2 ddr10c vdd2.5 gnd ddr9t ddr9c vdd2.5 pd# gnd ddr8t ddr8c vdd2.5 sel_ddr vdd2.5 gnd ddr11t ddr11c ddr10t gnd ddr6t ddr7t ddr7c gnd sclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 41 42 44 43 45 46 47 48 buf_in ddr1t_sdram0 ddr6c buf_in sdata sclk i2c control pd# ddr0t ddr0c ddr1t_sdram0 ddr1c_sdram1 ddr2t_sdram2 ddr2c_sdram3 ddr3t_sdram4 ddr3c_sdram5 ddr4t_sdram6 ddr4c_sdram7 ddr5t ddr5c ddr6t ddr6c ddr7t ddr7c ddr8t ddr8c ddr9t ddr9c ddr10t ddr10c ddr11t ddr11c
pll103-02 ddr sdram buffer for desktop pcs with 4 ddr dimms 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 11/07/00 page 2 pin descriptions name number type description fbout 1 o feedback clock for chipset. output voltage depends on vdd3.3_2.5v. buf_in 13 i reference input from chipset. 3.3v input for standard sdram mode ; 2.5v input for ddr-only mode. pd 36 i power down control input. when low, it will tri-state all outputs. sel_ddr 48 i input configure for ddr-only mode or standard sdram mode. 1 = ddr-only mode (when vdd3.3_2.5 select 2.5v); 0 = standard sdram mode (when vdd3.3_2.5 select 3.3v). in ddr-only mode, pin 4, 5, 6, 7, 10, 11, 15, 16, 19, 20, 21, 22, 27, 28, 29, 30, 33, 34, 38, 39, 42, 43, 44 and 45 will be configured as ddr outputs. in standard sdram mode, pin 6, 7, 11, 15, 16, 19 and 20 will be configured as standard sdram outputs. pin 27, 28, 29, 30, 33, 34, 38, 39, 42, 43, 44 and 45 will be configured as ddr outputs. pin 4, 5, 21 and 22 will be tri-stated. ddr[0,5:11]t 4,21,28,30,34, 39,43,45 o these outputs provide true copies of buf_in. ddr[0,5:11]c 5,22,27,29,33, 38,42,44 o these outputs provide complementary copies of buf_in. ddr[1:4]t_sdra m [0,2,4,6] 6,10,15,19 o when sel_ddr=1, these outputs provide ddr mode outputs; when sel_ddr=0, these outputs provide standard sdram mode outputs. voltage swing depends on vdd3.3_2.5. ddr[1:4]c_sdra m [1,3,5,7] 7,11,16,20 o when sel_ddr=1, these outputs provide complementary copies of buf_in; when sel_ddr=0, these outputs provide standard sdram mode outputs. voltage swing depends on vdd3.3_2.5. vdd3.3_2.5 2,8,12,17,23 p when vdd=2.5v, sel_ddr=1. ddr-only mode is selected ; when vdd=3.3v, sel_ddr=0. standard sdram mode is selected. vdd2.5 32,37,41,47 p 2.5v power supply. gnd 3,9,14,18,26, 31,35,40,46 p ground.
pll103-02 ddr sdram buffer for desktop pcs with 4 ddr dimms 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 11/07/00 page 3 address assignment a6 a5 a4 a3 a2 a1 a0 r/w 1 0 1 0 0 1 _ receiver/transmitter provides both slave write and data transfer rate standard mode at 100kbits/s this serial protocol is designed to allow both blocks write and read from the controller. the bytes must be accessed in sequential order from lowest to highest byte. each byte transferred terminate the transfer. the write or read block both begins with the master sending a slave address and a write condition (0xd2) or a read condition (0xd3). following the acknowledge of this address byte, in write mode: the command byte and byte count byte must be sent by the master but ignored by the slave, in read mode: the byte count byte will be read by the master then all other data byte . byte count byte default at power-up is = (0x09). i2c control registers 1. byte 6: outputs register (1=enable, 0=disable) bit pin# default description bit 7 48 1 sel_ddr ( i2c is ready only, value is set through pin48 ) bit 6 - 0 enhanced sdram drive. 1 = enhanced 25% bit 5 - 0 enhanced ddr drive. 1 = enhanced 25% bit 4 - 0 reserved bit 3 45, 44 1 ddr11t, ddr11c bit 2 43, 42 1 ddr10t, ddr10c bit 1 39, 38 1 ddr9t, ddr9c bit 0 34, 33 1 ddr8t, ddr8c
pll103-02 ddr sdram buffer for desktop pcs with 4 ddr dimms 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 11/07/00 page 4 2. byte 7: outputs register (1=enable, 0=disable) bit pin# default description bit 7 30, 29 1 ddr7t, ddr7c bit 6 28, 27 1 ddr6t, ddr6c bit 5 21, 22 1 ddr5t, ddr5c bit 4 19, 20 1 ddr4t_sdram6, ddr4c_sdram7 bit 3 15, 16 1 ddr3t_sdram4, ddr3c_sdram5 bit 2 10, 11 1 ddr2t_sdram2, ddr2c_sdram3 bit 1 6, 7 1 ddr1t_sdram0, ddr1c_sdram1 bit 0 4, 5 1 ddr0t, ddr0c
pll103-02 ddr sdram buffer for desktop pcs with 4 ddr dimms 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 11/07/00 page 5 electrical specifications 1. absolute maximum ratings parameters symbol min. max. units supply voltage v dd v ss - 0.5 7.0 v input voltage, dc v i v ss - 0.5 v dd + 0.5 v output voltage, dc v o v ss - 0.5 v dd + 0.5 v storage temperature t s -65 150 c ambient operating temperature t a 0 70 c esd voltage 2 kv exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device and affect product reliability. these conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. operating conditions parameters symbol min. max. units supply voltage v dd3.3 3.135 3.465 v supply voltage v dd2.5 2.375 2.625 v input capacitance c in 5 pf output capacitance c out 6 pf 3. electrical specifications parameters symbol conditions min. typ. max. units input high voltage v ih all inputs except i2c 2.0 v dd +0.3 v input low voltage v il all inputs except i2c v ss -0.3 0.8 v input high current i ih v in = v dd tbm ua input low current i il v in = 0 tbm ua output high voltage v oh iol = -12ma, vdd = 2.375v 1.7 v output low voltage v ol iol = 12ma, vdd = 2.375v 0.6 v output high current i oh vdd = 2.375v, vout=1v -18 -32 ma output low current i ol vdd = 2.375v, vout=1.2v 26 35 ma note: tbm: to be measured
pll103-02 ddr sdram buffer for desktop pcs with 4 ddr dimms 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 11/07/00 page 6 3. electrical specifications (continued) parameters symbol conditions min. typ. max. units supply current (ddr-only mode) i dd unloaded outputs, 133mhz tbm ma supply current (sdram mode) i dd unloaded outputs, 133mhz tbm ma supply current i dds pd = 0 tbm ma output crossing voltage v oc (vdd/2) -0.1 vdd/2 (vdd/2)+ 0.1 v output voltage swing v out 1.1 vdd-0.4 v duty cycle d t measured @ 1.5v 45 50 55 % max. operating frequency 66 170 mhz rising edge rate t or measured @ 0.4v ~ 2.4v 1.0 1.5 2.0 v/ns falling edge rate t of measured @ 2.4v ~ 0.4v 1.0 1.5 2.0 v/ns clock skew ( pin to pin ) t skew all outputs equally loaded 100 ps stabilization time t st 0.1 ms note: tbm: to be measured
pll103-02 ddr sdram buffer for desktop pcs with 4 ddr dimms 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 rev 11/07/00 page 7 package information ordering information phaselink corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. the information furnished by phaselink is believed to be accurate and reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of phaselink corporation. for part ordering, please contact our sales department: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination of the following: device number, package type and operating temperature range pll103-02 x c 0.008 - 0.016 (0.20 - 0.41) 0.620 - 0.630 (15.75 - 16.00) (0.25 - 0.41) 45 0 0.010 - 0.016 0.050 (1.346) min 3 0 -6 0 0.015 (0.381) 0.088 - 0.096 (2.250 - 2.450) 0.097 - 0.104 (2.467 - 2.642) 0.025 0.835 0.400 - 0.410 10.160 - 10.414 0.292 - 0.299 7.417 - 7.959 0.008 - 0.0135 0.203 - 0.343 48pin ssop part number temperaturature c=commercial m=military i=industral package type x=ssop
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